As the processing speed of microprocessors increases, the demand for memory devices having faster access times also increases. Additionally, the demand for memory devices that are designed for low voltage operation has also increased with the popularity of portable computing devices, which are typically battery operated. Memory system designers have developed methods and designs that shave off nanoseconds from access times in order to satisfy the demand for high speed memory devices while operating under low voltage conditions. Even with the advances made in memory device designs, the fundamental building blocks of memory devices have remained relatively the same. As will be described in more detail below, these building blocks are the basic elements that are shared among all types of memory devices, regardless of whether they are synchronous or asynchronous, random-access or read-only, or static or dynamic.
FIG. 1 illustrates an example memory device 110. As shown in the example of FIG. 1. The memory device includes an address register 112 that receives either a row address or a column address on an address bus 114. The address bus 114 is generally coupled to a memory controller (not shown). A row address is initially received by the address register 112 and applied to a row address multiplexer 118. The row address multiplexer 118 couples the row address to a number of components associated with either of two memory bank arrays, e.g., 120 and 122, depending upon the state of a bank address bit forming part of the row address. The arrays 120 and 122 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 120 and 122 is a respective row address latch 126, which stores the row address, and a row decoder 128, which applies various signals to its respective array 120 or 122 as a function of the stored row address.
After the row address has been applied to the address register 112 and stored in one of the row address latches 126, a column address is applied to the address register 112. The address register 112 couples the column address to a column address latch 140. The column address latch 140 momentarily stores the column address while it is provided to the column address buffer 144. The column address buffer 144 applies a column address to a column decoder 148, which applies various column signals to respective sense amplifiers and associated column circuits 150 and 152 for the respective arrays 120 and 122.
Data to be read from one of the arrays 120 or 122 are coupled from the arrays 120 or 122, respectively, to a data bus 158 through the column circuit 150 or 152, respectively, and a read data path that includes a data output buffer 156. Data to be written to one of the arrays 120 or 122 are coupled from the data bus 158 through a write data path, including a data input buffer 160, to one of the column circuits 150 or 152 where they are transferred to one of the arrays 120 or 122, respectively.
The above-described operation of the memory device 110 is controlled by a command decoder 168 responsive to high level command signals received on a control bus 170. These high level command signals, which are typically generated by the memory controller, are a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the “*” designates the signal as active low. The command decoder 168 generates a sequence of command signals responsive to the high level command signals to carry out a function, e.g., a read or a write operation, designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, will be appreciated by one of ordinary skill in the art. Further explanation is omitted so as not to obscure embodiments of the disclosure. As mentioned above, read data are coupled from one of the arrays 120 and 122 to the data bus 158 through a read data path, explained in more detail in connection with FIG. 2.
FIG. 2 illustrates an example data path 200 for a memory device, such as memory device 110 shown in FIG. 1. The data path 200 is coupled through a column decoder 248 and sense amplifiers 212 to a memory cell array 220 that is arranged in rows and columns of memory cells. Only one memory cell array 220 is illustrated in order to reduce the complexity of the drawing. However, embodiments are not so limited and, as shown in FIG. 1, more than one memory array, or bank of memory arrays, may be coupled to a particular column decoder 248. The sense amplifiers 212 shown in FIG. 2 may be included in the sense amplifiers and associated column circuits illustrated at 150 and 152 in FIG. 1.
Each of the columns of memory cells of the memory cell array 220 is represented by a pair of digit lines, e.g., 211, coupled to a respective one of the sense amplifiers 212. As known in the art, when the memory cell array 220 is accessed, a row of memory cells (not shown) are activated, and the sense amplifiers 212 amplify data by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have a complementary logic levels. The column decoder 248 then selects one of the columns of memory cells to be coupled to a local input/output (LIO) line 216 of the data path 200 based on a column address. The LIO 216 is represented by a pair of signal lines, e.g., 217A and 217B, each of which is coupled to a respective one of the pair of digit lines 211 by the column decoder 248. At the time the selected column is coupled to the LIO 216, the signal lines 217A and 217B of the LIO 216 are precharged to an internal supply voltage VINT for the memory cell array 220 through p-channel MOS (PMOS) transistors 220 and 222. A section selection signal SEC activates n-channel MOS (NMOS) pass gates 230 and 232 to couple the LIO 216 to global input/output (GIO) line 240. The GIO 240 is represented by a pair of signal lines, e.g., 241A and 241B, which are coupled to a respective one of the pair of signal lines 217A and 217B of the LIO 216. PMOS transistors 244 and 246 couple the signal lines 241A and 241B of the GIO 240 to the VINT supply of the array 220 for precharging. As discussed in more detail below, since the data path 200 is based on current mode sensing, the signal lines of the LIO 216 and the GIO 240 are coupled to the VINT supply to prevent significant voltage variations of the LIO 216 and GIO 240 when data read from the memory cell array 220 is coupled to the LIO 216 and GIO 240.
A current sense amplifier 250 is coupled to the GIO 240 to sense a current difference between the signal lines 241A and 241B of the GIO 240 and generate voltage output signals CLAT and CLAT_ (CLAT “bar”, also expressible as/CLAT or complementary latch) in response to the current difference. The output signals CLAT and CLAT_ have complementary logic levels, CLAT being the “true” logic level and CLAT_ being the “not true” logic level, as indicated by the underscore “_”, “/”, etc. The CLAT and CLAT_ signals are coupled to an output buffer to provide an output data signal at an external data terminal. The current sense amplifier 250 includes a pair of PMOS transistors 254, 256 for coupling respective signal lines of the GIO 240 to the VINT supply, and further includes a pair of cross coupled PMOS transistors 260, 264 and a pair of diode coupled NMOS transistors 270, 274 coupled to a drain of a respective PMOS transistor 260, 264. The CLAT and CLAT_ output signals are taken from output nodes 280, 284 corresponding to the drain of the PMOS transistors 260, 264. Coupled to the sources of the NMOS transistors 270, 274 is a NMOS selection transistor 280 for coupling the NMOS transistors 270, 274 to ground in response to an active selection signal SEL. It will be appreciated that FIG. 2 is provided by way of example, and other functional blocks have been omitted from the data path 200 to avoid overcomplicating the description of operating the data path 200.
In operation, when a memory cell is read, a selected pair of digit lines of a column of memory is coupled to the LIO 216 by the column decoder 248 and the pass-gates 230, 232 are activated to couple the LIO 216 to the GIO 240. A current difference is created in the pairs of signals lines in response to the data state of the memory cell being read. The current difference is detected by the current sense amplifier 250 by creating a current imbalance in the PMOS/diode coupled NMOS legs 260, 270 and 264, 274. The current imbalance results in a voltage difference at the respective output nodes 280, 284, which is further amplified as one of the cross coupled PMOS transistors 260, 264 becomes saturated and the other becomes cutoff. In this manner, the CLAT and CLAT_ signals achieve complementary logic levels.
The GIO lines 240 are physically long signal lines that are routed over the memory device to selectively couple, based on the selective activation of the SEC signal, physically shorter LIO lines 216 to a respective current sense amplifier 250. As a result, the GIO 240 have considerable line impedance that can significantly increase the time for sensing read data from the memory cell array 220 when voltage mode sensing is used. The current mode operation of the data path 200 has the advantage of avoiding the need to drive the signal lines of the GIO 240 to two voltage extremes as in the case for voltage mode sensing. Additionally, current mode operation allows for the voltage levels between the pairs of signal lines for the LIO 216, as well as the signal lines of the GIO 240, to be maintained at a relatively constant voltage. Thus, precharging and equilibrating time for the signal lines of the LIO 216, and of the GIO 240, can be shortened relative to memory devices employing voltage mode operation. As a result, access times can be shortened as well.
Current mode data paths, such as the data path 200, however, suffer when operated at low internal voltage levels. In order to operate properly, the data path 200 should have a VINT voltage level that is greater than the total voltage drop across the LIO 216, the GIO 240, and the PMOS/diode coupled NMOS legs 260, 270 or 264, 274. The voltage drop across the LIO 216 results from coupling a pair of digit lines to the respective signal lines of the LIO 216, and the voltage drop across the GIO 240 includes the voltage drop across the pass gates 230, 232, the precharge PMOS transistors 244, 246, and inherent line resistance of the typically lengthy signal lines of the GIO 240. The voltage drop across the PMOS/diode coupled NMOS legs 260, 270 or 264, 274, can be expressed as (Vtp+Vdpsat)+(Vtn+Vdnsat), where Vtp is the threshold voltage of the PMOS transistors 260, 264, Vdpsat is the saturation voltage of the PMOS transistors 260, 264, Vtn is the threshold voltage of the NMOS transistors 270, 274, and Vtnsat is the saturation voltage of the NMOS transistors 270, 274.
When using typical operating currents and device characteristics for the data path 200, operation at a voltage level of 1.5 volts is satisfactory. However, where it is desirable to implement the data path 200 under operating conditions having voltage levels approaching 1.0 volts, the data path 200 may not consistently or accurately sense data read from the memory cell array 220. As a result, a read error occurs. Therefore, there is a need for a data path that can accurately and consistently sense read data under low voltage operating conditions.